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Disambiguation of "Yang, Zunsong"

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A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3991-4004 (2019)

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Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

 

Other publications of authors with the same name

Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit., , , , , , , and . ICICDT, page 92-95. IEEE, (2023)A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur., , , , and . ISSCC, page 270-272. IEEE, (2019)A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector., , , , and . IEEE Access, (2020)A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS., , , and . A-SSCC, page 283-284. IEEE, (2019)A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter., , , and . VLSI Technology and Circuits, page 10-11. IEEE, (2022)A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3991-4004 (2019)A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit., , , , , , , and . ICICDT, page 88-91. IEEE, (2023)7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur., , , , and . ISSCC, page 130-132. IEEE, (2024)A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering., , , and . IEEE J. Solid State Circuits, 59 (7): 2171-2184 (July 2024)