Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, Y. Ma, H. Shen, S. Fukami, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu. VLSI Circuits, page 1-2. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Natsui, Masanori

add a person with the name Natsui, Masanori

Other publications of authors with the same name

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno. Proc. IEEE, 104 (10): 1844-1863 (2016)Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network.K. Asano, M. Natsui, and T. Hanyu. ICECS, page 1-4. IEEE, (2023)Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme.H. Shirahama, T. Matsuura, M. Natsui, and T. Hanyu. IEICE Trans. Inf. Syst., 93-D (8): 2080-2088 (2010)Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission.N. Sugaya, M. Natsui, and T. Hanyu. ISMVL, page 72-77. IEEE Computer Society, (2016)Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System.T. Matsuura, H. Shirahama, M. Natsui, and T. Hanyu. ISMVL, page 60-65. IEEE Computer Society, (2009)Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui. DATE, page 548-553. IEEE, (2017)Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system.M. Natsui, and T. Hanyu. NEWCAS, page 97-100. IEEE, (2012)Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI.M. Natsui, and T. Hanyu. NEWCAS, page 468. IEEE, (2014)VLSI circuit design using an object-oriented framework of evolutionary graph generation system.N. Homma, M. Natsui, T. Aoki, and T. Higuchi. IEEE Congress on Evolutionary Computation, page 115-122. IEEE, (2003)Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction.H. Suda, M. Natsui, and T. Hanyu. ISMVL, page 56-61. IEEE Computer Society, (2018)

BibSonomy

Disambiguation of "Natsui, Masanori"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Natsui, Masanori"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.