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Machine learning resistant strong PUF: Possible or a pipe dream?

, , , and . HOST, page 19-24. IEEE Computer Society, (2016)

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Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits., , , and . ACM Great Lakes Symposium on VLSI, page 265-270. ACM, (2011)On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery., , and . ISVLSI, page 510-515. IEEE Computer Society, (2014)A Chaotic Ring oscillator based Random Number Generator., , and . HOST, page 160-165. IEEE Computer Society, (2014)An Efficient Method for Clock Skew Scheduling to Reduce Peak Current., , and . VLSID, page 505-510. IEEE Computer Society, (2016)On meta-obfuscation of physical layouts to conceal design characteristics., , and . DFT, page 147-152. IEEE Computer Society, (2016)A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics., and . DATE, page 653-658. ACM, (2015)Glitch Power Reduction via Clock Skew Scheduling., and . ISVLSI, page 504-509. IEEE Computer Society, (2014)A system-level solution for managing spatial temperature gradients in thinned 3D ICs., , , and . ISQED, page 88-95. IEEE, (2013)Preventing integrated circuit piracy via custom encoding of hardware instruction set., , and . ISQED, page 234-241. IEEE, (2016)On pattern generation for maximizing IR drop., , , and . ISQED, page 731-737. IEEE, (2014)