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Disambiguation of "Katoch, Atul"

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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

, , , , , , , , , , , , , and . ISSCC, page 210-211. IEEE, (2017)

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Atul Luykx

Atul Kumar

Atul Suresh Deshpande

Atul Kumar Agarwala

 

Other publications of authors with the same name

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications., , , , , , , , , and 4 other author(s). ISSCC, page 210-211. IEEE, (2017)A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 270-271. IEEE, (2008)Isodelay output driver design using step-wise charging for low power., and . ESSCIRC, page 149-152. IEEE, (2005)Aggressor aware repeater circuits for improving on-chip bus performance and robustness., , and . ESSCIRC, page 261-264. IEEE, (2003)High speed current-mode signaling circuits for on-chip interconnects., , and . ISCAS (4), page 4138-4141. IEEE, (2005)Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems., , , , and . IOLTS, page 135-140. IEEE Computer Society, (2004)New ECC for Crosstalk Impact Minimization., , , and . IEEE Des. Test Comput., 22 (4): 340-348 (2005)Reducing Cross-Talk Induced Power Consumption and Delay., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 179-188. Springer, (2004)Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity., , , and . ESSCIRC, page 323-326. IEEE, (2004)A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)