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Disambiguation of "Mitsuyama, Yukio"

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Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems.

, , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (4): 899-906 (2005)

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Yukio Matsudo

Yukio Yamanaka

Yukio Kamizuru

Yukio Ozawa

 

Other publications of authors with the same name

NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (7): 1483-1491 (2014)Area-Efficient Reconfigurable Architecture for Media Processing., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3651-3662 (2008)Measurement of Variations in FPGAs under Various Load Conditions., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2020)VLSI architecture of dynamically reconfigurable hardware-based cipher., , , and . ISCAS (4), page 734-737. IEEE, (2001)A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture., , , , , and . FPL, page 615-618. IEEE, (2012)Burst mode: a new acceleration mode for 128-bit block ciphers., , , and . CICC, page 151-154. IEEE, (2002)Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 333-343 (2012)Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars., , , , , , , , , and 6 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2723-2736 (2018)Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture., , , , , , , , , and 4 other author(s). IEEE Embed. Syst. Lett., 10 (4): 119-122 (2018)A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling., , , and . IEEE Trans. Inf. Forensics Secur., 8 (8): 1331-1342 (2013)