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Processing and Scheduling Components in an Innovative Network Processor Architecture., , , , , , , and . VLSI Design, page 195-201. IEEE Computer Society, (2003)Hardware-assisted dynamic power and thermal management in multi-core SoCs., and . ACM Great Lakes Symposium on VLSI, page 115-120. ACM, (2011)On the Importance of Header Classification in HW/SW Network Intrusion Detection Systems., , and . Panhellenic Conference on Informatics, volume 3746 of Lecture Notes in Computer Science, page 661-671. Springer, (2005)An FPGA-based high-throughput stream join architecture., , , and . FPL, page 1-4. IEEE, (2016)A rate-based prefiltering approach to blast acceleration., , , , and . FPL, page 631-634. IEEE, (2008)Hashing + Memory = Low Cost, Exact Pattern Matching., and . FPL, page 39-44. IEEE, (2005)Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems., , , , , , , , and . ARC, volume 14553 of Lecture Notes in Computer Science, page 19-32. Springer, (2024)A Systematic Evaluation of Emerging Mesh-like CMP NoCs., , , , , , and . ANCS, page 159-170. IEEE Computer Society, (2015)EDRA: A Hardware-Assisted Decoupled Access/Execute Framework on the Digital Market - Invited Paper., , , and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 319-330. Springer, (2021)RACOS: Transparent access and virtualization of reconfigurable hardware accelerators., and . SAMOS, page 11-19. IEEE, (2017)