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Processing and Scheduling Components in an Innovative Network Processor Architecture.

, , , , , , , and . VLSI Design, page 195-201. IEEE Computer Society, (2003)

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Efficient modeling of VBR MPEG-1 coded video sources., , , and . IEEE Trans. Circuits Syst. Video Techn., 10 (1): 93-112 (2000)An innovative scheduling scheme for high-speed network processors., , , , , and . ISCAS (2), page 93-96. IEEE, (2003)An efficient shared-buffer for high speed ATM networks., , , and . ICECS, page 776-779. IEEE, (1996)Transfer of data over ATM networks using available bit rate (ABR)., and . ISCC, page 2-8. IEEE Computer Society, (1995)SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images., , , , , , and . VLSI-SoC, page 1-4. IEEE, (2022)Integrated signalling functionality for multimedia services., , , , , and . ISCC, page 91-95. IEEE Computer Society, (1997)High performance ATM terminals: design and evaluation., and . Modelling and Evaluation of ATM Networks, volume 17 of IFIP Conference Proceedings, page 596-618. Chapman & Hall, (1994)Performance Models for Multiplexed VBR MPEG Video Sources., , , and . ICC (2), page 856-861. IEEE, (1997)Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units., , , , , , and . Microprocess. Microsystems, 31 (3): 188-199 (2007)An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems., , , , , and . ICECS, page 93-96. IEEE, (1999)