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Quantifying observability for in-system debug of high-level synthesis circuits.

, and . FPL, page 1-11. IEEE, (2016)

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Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs., and . FPT, page 354-357. IEEE, (2018)Improving the Reliability of FPGA CRO PUFs., , , and . FPL, page 311-316. IEEE, (2023)Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs., and . FPT, page 40-47. IEEE, (2015)Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (1): 83-96 (2017)Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis., and . ReConFig, page 1-5. IEEE, (2019)Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques., , and . FPL, page 1-4. IEEE, (2017)Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison., , and . ICFPT, page 142-151. IEEE, (2023)Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices.. FCCM, page 136-143. IEEE Computer Society, (2017)Architecture Exploration for HLS-Oriented FPGA Debug Overlays., , and . FPGA, page 209-218. ACM, (2018)Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF., , , , and . FPT, page 1-10. IEEE, (2022)