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A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs., , , , and . Microelectron. J., 40 (6): 952-957 (2009)Power supply noise and logic error probability., , , , and . ECCTD, page 152-155. IEEE, (2007)Analysis of delay mismatching of digital circuits caused by common environmental fluctuations., , , and . ISCAS, page 2585-2588. IEEE, (2011)New redundant logic design concept for high noise and low voltage scenarios., , , , , and . Microelectron. J., 42 (12): 1359-1369 (2011)Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K., , , , , , , , , and 2 other author(s). ISCAS, page 1-5. IEEE, (2020)Understanding complexity in multiphysics systems-on-a-chip: Modern approaches for design., , , , , , , and . ISCAS, page 1546-1549. IEEE, (2015)Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures., , , , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Modelling of Electron Injection and Confinement in Cryogenic 22-nm FD-SOI Quantum Dot Arrays., , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI., , , , , , , , and . ESSCIRC, page 47-50. IEEE, (2021)