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A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs.

, , , , and . Microelectron. J., 40 (6): 952-957 (2009)

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PVTA Tolerant Self-adaptive Clock Generation Architecture., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 142-154. Springer, (2012)Analysis of delay mismatching of digital circuits caused by common environmental fluctuations., , , and . ISCAS, page 2585-2588. IEEE, (2011)Novel redundant logic design for noisy low voltage scenarios., , , and . LASCAS, page 1-4. IEEE, (2013)High level spectral-based analysis of power consumption in DSPs systems., , and . ISCAS, IEEE, (2006)Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact., , , and . IEEE Access, (2022)New redundant logic design concept for high noise and low voltage scenarios., , , , , and . Microelectron. J., 42 (12): 1359-1369 (2011)Two examples of approximate arithmetic to reduce hardware complexity and power consumption., , , , , , , , and . DCIS, page 1-6. IEEE, (2022)Variation tolerant self-adaptive clock generation architecture based on a ring oscillator., , and . SoCC, page 387-392. IEEE, (2012)A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs., , , , and . Microelectron. J., 40 (6): 952-957 (2009)A single event transient hardening circuit design technique based on strengthening., , , and . MWSCAS, page 821-824. IEEE, (2013)