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Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning.

, , , and . Sci. China Inf. Sci., 62 (6): 62408:1-62408:19 (2019)

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The synthesis method of logic circuits based on the iMemComp gates., , , , , and . Integr., (2020)A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient., , , , , , , , , and . ISCAS, page 1-4. IEEE, (2018)Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning., , , and . Sci. China Inf. Sci., 62 (6): 62408:1-62408:19 (2019)FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network., , , , , , , and . ASICON, page 1-4. IEEE, (2019)A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization., , , , , and . DAC, page 1-6. IEEE, (2023)Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture., , , , , , , , , and . ISCAS, page 417-420. IEEE, (2014)Parameters extraction on HfOX based RRAM., , , , , , and . ESSDERC, page 250-253. IEEE, (2014)Physical understanding and optimization of resistive switching characteristics in oxide-RRAM., , , , , , , , , and . ESSDERC, page 154-159. IEEE, (2016)RRAM based synaptic devices for neuromorphic visual systems., , , , , , , and . DSP, page 1219-1222. IEEE, (2015)Design guidelines for 3D RRAM cross-point architecture., , , , , , , , , and . ISCAS, page 421-424. IEEE, (2014)