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Doppelganger: A Cache for Approximate Computing

, , , and . In Proceedings of the International Symposium on Microarchitecture, (2015)

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Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks., , , and . CoRR, (2017)Practical off-chip meta-data for temporal memory streaming., , , , and . HPCA, page 79-90. IEEE Computer Society, (2009)Characterizing the performance benefits of fused CPU/GPU systems using FusionSim., , and . DATE, page 685-688. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Slice-processors: an implementation of operation-based prediction., , and . ICS, page 321-334. ACM, (2001)Two-Stage, Pipelined Register Renaming., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1926-1931 (2011)A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy., , and . MICRO, page 314-327. IEEE Computer Society, (2007)Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator., and . HiPEAC, volume 4917 of Lecture Notes in Computer Science, page 258-272. Springer, (2008)JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers., , , and . HPCA, page 85-96. IEEE Computer Society, (2001)Prediction-based superpage-friendly TLB designs., , , and . HPCA, page 210-222. IEEE Computer Society, (2015)Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors., and . ICCD, page 458-461. IEEE Computer Society, (2002)