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Disambiguation of "Chen, Hung-Ming"

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Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.

, , , and . DATE, page 845-850. IEEE, (2009)

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Ming Chen

Ming Chen

Ming Chen

Ming Chen

Ming Chen

 

Other publications of authors with the same name

Solving Large Knowledge Base Partitioning Problems Using an Intelligent Genetic Algorithm, , and . Proceedings of the Genetic and Evolutionary Computation Conference, 2, page 1567--1572. Orlando, Florida, USA, Morgan Kaufmann, (13-17 July 1999)On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study., and . SoCC, page 203-206. IEEE, (2006)Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design., , , and . SoCC, page 211-214. IEEE, (2006)Mixed non-rectangular block packing for non-Manhattan layout architectures., , and . ISQED, page 257-262. IEEE, (2011)Cost-effective decap selection for beyond die power integrity., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits., , and . J. Inf. Sci. Eng., 27 (1): 287-302 (2011)A learning-based methodology for routability prediction in placement., , , and . VLSI-DAT, page 1-4. IEEE, (2018)Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations., and . ISPD, page 23-30. ACM, (2008)On the way to practical tools for beyond die codesign and integration.. ISPD, page 61. ACM, (2013)More Effective Power Network Prototyping by Analytical and Centroid Learning., , , , and . ISCAS, page 1-5. IEEE, (2019)