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A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.

C. Cheng, J. Wang, P. Chou, S. Chen, C. Sun, Y. Chu, and T. Yang. A-SSCC, page 361-364. IEEE, (2014)

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Chun Yuan

Yuan-Chung Cheng

Yu-Chun Yuan

Cheng-Chun Lu

Chun Hung Cheng

Other publications of authors with the same name

Applying Particle Swarm Optimization algorithm to roundness measurement.C. Cheng, C. Lo, C. Chiang, and F. Tien. SMC, page 2766-2770. IEEE, (2007)A 55nm 1GHz one-cycle-locking de-skewing circuit.J. Wang, C. Cheng, J. Liu, Y. Liu, and Y. Wang. ISCAS, page 1755-1758. IEEE, (2010)An improved SAR controller for DLL applications.J. Wang, Y. Wang, C. Cheng, and Y. Liu. ISCAS, IEEE, (2006)The Near-Optimal Preventive Maintenance Policies for a Repairable System with a Finite Life Time by Using Simulation Methods.C. Cheng. J. Comput., 6 (3): 548-555 (2011)Roundness measurement using the PSO algorithm.T. Sun, C. Cheng, and F. Tien. ICNC, page 1202-1206. IEEE, (2011)L1-Normed GM(1, 1) Models and Reliability Analysis.R. Guo, C. Cheng, and Y. Cui. SMC, page 775-779. IEEE, (2006)Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.C. Cheng, J. Wang, C. Yeh, and J. Sheu. VLSIC, page 186-187. IEEE, (2012)The Periodic Maintenance Policy for a Weibull Life-Time System with Degradation Rate Reduction under Reliability Limit.C. Cheng, and M. Chen. Asia Pac. J. Oper. Res., 25 (6): 793-805 (2008)IISR Crosslink Approach at NTCIR 9 CLLD Task.C. Cheng, Y. Wang, and R. Tsai. NTCIR, National Institute of Informatics (NII), (2011)ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.J. Wang, Y. Chien, J. Lin, C. Cheng, Y. Ma, and C. Huang. ASICON, page 47-50. IEEE, (2011)

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Disambiguation of "Cheng, Chun-Yuan"

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A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.

Please choose a person to relate this publication to

Chun Yuan

Yuan-Chung Cheng

Yu-Chun Yuan

Cheng-Chun Lu

Chun Hung Cheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cheng, Chun-Yuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.

Please choose a person to relate this publication to

Chun Yuan

Yuan-Chung Cheng

Yu-Chun Yuan

Cheng-Chun Lu

Chun Hung Cheng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.