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An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications., , , and . APCCAS, page 500-503. IEEE, (2010)A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC., , , , , and . ISSCC, page 184-595. IEEE, (2007)A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE., , , and . VLSI Circuits, page 1-2. IEEE, (2016)A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison., , , , and . Journal of Circuits, Systems, and Computers, (2012)A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 904-908 (March 2023)Low Power Cache with Successive Tag Comparison Algorithm., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 599-606. Springer, (2003)A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process., , , , and . ASP-DAC, page 89-90. IEEE, (2013)A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1461-1469 (2009)A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 331-342 (2018)A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (10): 1207-1211 (2017)