Author of the publication

Limit cycle counting based smart background calibration of continuous time sigma delta ADCs.

, , , and . ISCAS, page 722-725. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A106nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS., , , , and . IEEE J. Solid State Circuits, 51 (10): 2435-2445 (2016)Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator., , , and . IEEE J. Solid State Circuits, 37 (5): 657-661 (2002)A wide-tunable translinear second-order oscillator., , , and . IEEE J. Solid State Circuits, 33 (2): 195-201 (1998)A reduced-area low-power low-voltage single-ended differential pair., , and . IEEE J. Solid State Circuits, 32 (2): 254-257 (1997)An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids., , , and . IEEE J. Solid State Circuits, 33 (2): 291-294 (1998)A design methodology for power-efficient reconfigurable SC ΔΣ modulators., , , , , , and . Int. J. Circuit Theory Appl., 43 (8): 1024-1041 (2015)Design of Optimal Dynamic Range Integrated Mixer-Filter Systems., , , and . ISCAS, page 261-264. IEEE, (1994)Extended modelling for time-encoding converters., , , and . ISCAS, page 1077-1080. IEEE, (2010)Analytical passive mixer power gain models., , , , and . ISCAS, page 2386-2389. IEEE, (2010)Low voltage, low power folded-switching mixer with current-reuse in 0.18µm CMOS., , , , and . ISCAS (1), page 569-72. IEEE, (2004)