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Fastpath: A Path-Delay Test Generator for Standard Scan Designs.

, , , and . ITC, page 154-163. IEEE Computer Society, (1994)

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DFFT : Design For Functional Testability., and . ITC, page 1105-1114. IEEE Computer Society, (2003)DFT and Test Problems from the Trenches.. VTS, page 120. IEEE Computer Society, (2009)A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm., and . DAC, page 77-83. IEEE Computer Society Press, (1990)Fault simulation of interconnect opens in digital CMOS circuits.. ICCAD, page 548-554. IEEE Computer Society / ACM, (1997)Validation and Test of Network Processors and ASICs., , , , and . VTS, page 407-410. IEEE Computer Society, (2002)Voltage- and current-based fault simulation for interconnect open defects.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (12): 1768-1779 (1999)On invalidation mechanisms for non-robust delay tests.. ITC, page 393-399. IEEE Computer Society, (2000)Explorations of sequential ATPG using Boolean satisfiability., and . VTS, page 85-90. IEEE Computer Society, (1993)Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop Testing.. VTS, page 33-38. IEEE Computer Society, (2009)Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits., and . ITC, page 597-606. IEEE Computer Society, (1997)