( en | de | ru )

 

Disambiguation of "Becker, Jürgen"

Author of the publication

copydeleteadd this publication to your clipboard
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems.

, , , , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 96-111. Springer, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jürgen Becker

Jürgen Becker

Jürgen Becker

Jürgen Becker

Jürgen Becker

 

Other publications of authors with the same name

A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems., , and . IPPS/SPDP Workshops, volume 1388 of Lecture Notes in Computer Science, page 61-66. Springer, (1998)A Secure Framework with Remote Configuration of Intellectual Property., , and . ICISSP, page 564-571. SciTePress, (2019)SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators., , , , , and . ACM Great Lakes Symposium on VLSI, page 287-292. ACM, (2023)Work-in-Progress: Integrating WebAssembly into Service-Oriented Architectures for Edge Systems., , , and . EMSOFT, page 17-18. ACM / IEEE, (2023)Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen., , , , , , and . MECO, page 1-4. IEEE, (2022)Energy Model of Networks-on-Chip and a Bus., , , , and . SoC, page 82-85. IEEE, (2005)Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology., , , and . FPT, page 165-173. IEEE, (2020)Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors., , , , , and . SOCC, page 1-6. IEEE, (2022)Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development., , and . SOCC, page 1-2. IEEE, (2022)Non-Intrusive Runtime Monitoring for Manycore Prototypes., , , and . DroneSE/RAPIDO@HiPEAC, page 31-38. ACM, (2023)