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Novel SRAM bias control circuits for a low power L1 data cache.

A. Seyedi, A. Armejach, A. Cristal, O. Unsal, and M. Valero. NORCHIP, page 1-6. IEEE, (2012)

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Adrián Granada

Adrián Juárez

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

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Vector Extensions for Decision Support DBMS Acceleration.T. Hayes, O. Palomar, O. Unsal, A. Cristal, and M. Valero. MICRO, page 166-176. IEEE Computer Society, (2012)Atomic quake: using transactional memory in an interactive multiplayer game server.F. Zyulkyarov, V. Gajinov, O. Unsal, A. Cristal, E. Ayguadé, T. Harris, and M. Valero. PPoPP, page 25-34. ACM, (2009)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.A. Armejach, A. Seyedi, J. Gil, I. Hur, A. Cristal, O. Unsal, and M. Valero. PACT, page 361-371. IEEE Computer Society, (2011)STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.G. Kestor, R. Gioiosa, T. Harris, O. Unsal, A. Cristal, I. Hur, and M. Valero. PACT, page 221-231. IEEE Computer Society, (2011)VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes.S. Rethinagiri, O. Palomar, J. Moreno, O. Unsal, and A. Cristal. ICCD, page 651-658. IEEE Computer Society, (2015)FIMSIM: A fault injection infrastructure for microarchitectural simulators.G. Yalcin, O. Unsal, A. Cristal, and M. Valero. ICCD, page 431-432. IEEE Computer Society, (2011)RETHINK big: European roadmap for hardware anc networking optimizations for big data.G. Alioto, P. Carpenter, A. Cristal, O. Unsal, M. Leich, and C. Avare. DATE, page 121-126. IEEE, (2017)Verification Tools for Transactional Programs.A. Cristal, B. Ozkan, E. Cohen, G. Kestor, I. Kuru, O. Unsal, S. Tasiran, S. Mutluergil, and T. Elmas. Transactional Memory, volume 8913 of Lecture Notes in Computer Science, Springer, (2015)T-Rex: a dynamic race detection tool for C/C++ transactional memory applications.G. Kestor, O. Unsal, A. Cristal, and S. Tasiran. EuroSys, page 20:1-20:12. ACM, (2014)Programmer-directed partial redundancy for resilient HPC.O. Subasi, J. Moreno, O. Unsal, J. Labarta, and A. Cristal. Conf. Computing Frontiers, page 47:1-47:2. ACM, (2015)

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Disambiguation of "Cristal, Adrián"

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Novel SRAM bias control circuits for a low power L1 data cache.

Please choose a person to relate this publication to

Adrián Granada

Adrián Juárez

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cristal, Adrián"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Novel SRAM bias control circuits for a low power L1 data cache.

Please choose a person to relate this publication to

Adrián Granada

Adrián Juárez

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Novel SRAM bias control circuits for a low power L1 data cache.