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Circuit design of a dual-versioning L1 data cache for optimistic concurrency., , , , , and . ACM Great Lakes Symposium on VLSI, page 325-330. ACM, (2011)Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications., , and . NORCAS, page 1-6. IEEE, (2019)Flexicache: Highly Reliable and Low Power Cache under Supply Voltage Scaling., , , and . CARLA, volume 485 of Communications in Computer and Information Science, page 173-190. Springer, (2014)Circuit design of a novel adaptable and reliable L1 data cache., , , and . ACM Great Lakes Symposium on VLSI, page 333-334. ACM, (2013)Circuit designs for increasing reliability and reducing energy.. Polytechnic University of Catalonia, Spain, (2016)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory., , , , , , and . PACT, page 361-371. IEEE Computer Society, (2011)NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs., , , , , and . NANOARCH, page 51-56. IEEE Computer Society, (2015)