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IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.

, , and . Asian Test Symposium, page 375-. IEEE Computer Society, (1999)

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VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (4): 541-556 (1986)The CDB/HCDB semiconductor wafer representation server., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (2): 283-295 (1993)Power Supply Noise in Delay Testing., , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Optimal voltage testing for physically-based faults., and . VTS, page 344-353. IEEE Computer Society, (1996)Improvement of SRAM-based failure analysis using calibrated Iddq testing., and . VTS, page 130-137. IEEE Computer Society, (1996)FedEx - a fast bridging fault extractor., and . ITC, page 696-703. IEEE Computer Society, (2001)Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits., and . VTS, page 70-79. IEEE Computer Society, (1999)Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors., and . DFT, page 140-. IEEE Computer Society, (2003)A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator., , and . DAC, page 579-584. ACM, (1991)Bridging Fault Detection in FPGA Interconnects Using IDDQ., , and . FPGA, page 95-104. ACM, (1998)