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Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor., , and . International Conference on Supercomputing, page 220-229. ACM, (1993)Limits of Thread-Level Parallelism in Non-numerical Programs., , , and . Inf. Media Technol., 1 (2): 851-859 (2006)Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation., , , and . MEDEA@PACT, page 33-40. ACM, (2007)A preactivating mechanism for a VT-CMOS cache using address prediction., , , , and . ISLPED, page 247-250. ACM, (2002)Pipeline stage unification: a low-energy consumption technique for future mobile processors., , and . ISLPED, page 326-329. ACM, (2003)Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors., , , and . ICPP, page 584-591. IEEE Computer Society Press, (1986)The Hardware Architecture of the CODA Real-Time Parallel Processor., , , and . PARCO, page 395-402. Elsevier, (1993)Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations., , , and . ISCA, page 226-234. IEEE Computer Society, (1986)Efficient vector processing on dataflow supercomputer SIGMA-1., , and . SC, page 374-381. IEEE Computer Society, (1988)An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism., , , , and . EUROMICRO, page 1432-1440. IEEE Computer Society, (1999)