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Disambiguation of "Ecker, Wolfgang"

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Special Session: Machine Learning for Embedded System Design.

, , , , , , , , , , and . CODES+ISSS, page 28-37. IEEE, (2023)

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Wolfgang Ecker

Wolfgang Ecker

Wolfgang Ecker

Wolfgang Ecker

Werner Ecker

 

Other publications of authors with the same name

Digital Hardware Design Based on Metamodels and Model Transformations., and . VLSI-SoC (Selected Papers), volume 508 of IFIP Advances in Information and Communication Technology, page 83-107. Springer, (2016)MetaFS: Model-driven Fault Simulation Framework., , , , , , and . DFT, page 1-4. IEEE, (2022)Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation., , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations., , and . EURO-DAC, page 624-629. IEEE Computer Society, (1994)G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators., , , , , , , , , and 2 other author(s). DAC, page 1-6. IEEE, (2023)Design centric modeling of digital hardware., , and . HLDVT, page 46-52. IEEE, (2016)A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications., , , and . DSD, page 413-420. IEEE Computer Society, (2018)Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation., , , , and . MCSoC, page 508-515. IEEE, (2023)Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs., , , and . ISQED, page 1-8. IEEE, (2024)Efficient handling of the fault space in functional safety analysis utilizing formal methods., , and . VLSI-SoC, page 1-7. IEEE, (2016)