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A Flexible Datapath Interconnect for Embedded Applications.

, , and . ISVLSI, page 15-20. IEEE Computer Society, (2007)

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DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures., , and . Applied Informatics, page 767-772. IASTED/ACTA Press, (2003)Manufacturable nanometer designs using standard cells with regular layout., and . ISQED, page 398-405. IEEE, (2013)Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication., , and . ICECS, page 45-48. IEEE, (2019)Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree., , , , , , and . ICECS, page 77-80. IEEE, (2009)Time-domain interconnect characterisation flow for appropriate model segmentation., , and . IET Comput. Digit. Tech., 2 (4): 265-274 (2008)GLMC: interconnect length estimation by growth-limited multifold clustering., , and . ISCAS, page 465-468. IEEE, (2000)Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits., , and . ISLPED, page 245-249. ACM, (1998)An Efficient Twin-Precision Multiplier., , and . ICCD, page 30-33. IEEE Computer Society, (2004)Application-Specific Energy Optimization of General-Purpose Datapath Interconnect., , , and . ISVLSI, page 301-306. IEEE Computer Society, (2011)Interconnect-Driven Short-Circuit Power Modeling., and . DSD, page 414-421. IEEE Computer Society, (2001)