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An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOS.

, , , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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Verification of Digital RF Processors: RF, Analog, Baseband, and Software., , and . IEEE J. Solid State Circuits, 42 (5): 992-1002 (2007)Design Considerations for Terahertz Wireless Communication Systems., , , , , and . WCNC Workshops, page 1-5. IEEE, (2020)A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels., , and . IEEE J. Solid State Circuits, 35 (8): 1205-1210 (2000)Decision feedback equalizer with two's complement computation sharing multiplication., , and . ICASSP, page 1245-1248. IEEE, (2001)Minimally redundant parallel implementation of digital filters and vector scaling., and . ICASSP, page 3295-3298. IEEE, (2000)MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters., , and . DATE, page 10700-10705. IEEE Computer Society, (2003)A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS., , , , , , , , , and 23 other author(s). ISSCC, page 208-209. IEEE, (2008)A 3-5 GHz Current-Reuse gm-Boosted CG LNA for Ultrawideband in 130 nm CMOS., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (3): 400-409 (2012)Efficient generation of 1/fα noise using a multi-rate filter bank., , and . CICC, page 707-710. IEEE, (2003)A novel design methodology for high performance and low power digital filters., and . ICCAD, page 80-83. IEEE Computer Society, (1999)