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Disambiguation of "Mohanty, Basant K."

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Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems.

, , and . DSP, page 1266-1269. IEEE, (2015)

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Jitendranath Mohanty

Subhasis Mohanty

Sasank Sekhar Mohanty

Basant Kumar Thakur

Jyoti Ranjan Mohanty

 

Other publications of authors with the same name

Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic., and . APCCAS, page 1195-1198. IEEE, (2010)Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT., and . IEEE Trans. Circuits Syst. Video Techn., 20 (9): 1200-1209 (2010)Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems., , , and . DSP, page 1270-1273. IEEE, (2015)Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT., and . IEEE Trans. Signal Process., 59 (5): 2072-2084 (2011)Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform., , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (2): 151-155 (2008)Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data., and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (3): 1042-1050 (2019)A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage., and . Turkish J. Electr. Eng. Comput. Sci., 31 (7): 1237-1254 (November 2023)Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems., , and . DSP, page 1266-1269. IEEE, (2015)Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames., and . IEEE Trans. Signal Process., 59 (11): 5605-5616 (2011)Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits., , and . ISCAS, page 2628-2631. IEEE, (2014)