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High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.

, , , , , , , , , , , , , , and . DFT, page 121-125. IEEE Computer Society, (2012)

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CMOS Self Checking Circuits with Faulty Sequential Functional Block., , and . DFT, page 133-141. IEEE Computer Society, (1994)A Highly Testable 1-out-of-3 CMOS Checker., , , and . DFT, page 279-286. IEEE Computer Society, (1993)On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values., , and . DATE, page 763. IEEE Computer Society / ACM, (2000)Optimization of error detecting codes for the detection of crosstalk originated errors., and . DATE, page 290-296. IEEE Computer Society, (2001)Embedded two-rail checkers with on-line testing ability., , and . VTS, page 145-150. IEEE Computer Society, (1996)Checker No-Harm Alarm Robustness., , , and . IOLTS, page 275-280. IEEE Computer Society, (2006)Hardware Reconfiguration Scheme for High Availability Systems., , , and . IOLTS, page 161-166. IEEE Computer Society, (2004)Coding Scheme for Low Energy Consumption Fault-Tolerant Bus., , , , and . IOLTW, page 8-12. IEEE Computer Society, (2002)Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures., and . IOLTW, page 100-105. IEEE Computer Society, (2001)Fast and Low-Cost Clock Deskew Buffer., , and . DFT, page 202-210. IEEE Computer Society, (2004)