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Low power design for SoC with power management unit., , , , и . ASICON, стр. 719-722. IEEE, (2011)A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control., , , , и . ASICON, стр. 870-873. IEEE, (2011)A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures., , , , и . IEICE Trans. Inf. Syst., 96-D (3): 616-623 (2013)An Analytical Model for Domain-Specific Accelerator Deploying Sparse LU Factorization., , и . ASICON, стр. 1-4. IEEE, (2023)14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS., , , , , , , , и . ISSCC, стр. 230-232. IEEE, (2020)Domain Strategy and Coverage Metric for Validation., , , , и . ISQED, стр. 40-45. IEEE Computer Society, (2005)A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects., , , , , и . DATE, стр. 1-6. IEEE, (2024)Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation., , , , , и . DAC, стр. 150. ACM, (2019)TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages., , , , , , и . CoRR, (2019)A novel surface potential-based short channel MOSFET model for circuit simulation., , и . Microelectron. J., 42 (10): 1169-1175 (2011)