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Sensing margin trend with technology scaling in MRAM.

, , , , and . I. J. Circuit Theory and Applications, 39 (3): 313-325 (2011)

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A methodology for statistical estimation of read access yield in SRAMs., , , , , and . DAC, page 205-210. ACM, (2008)A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V., , , , , , , , , and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors., , , , , , , and . ITC, page 1. IEEE Computer Society, (2014)A robust single supply voltage SRAM read assist technique using selective precharge., , and . ESSCIRC, page 234-237. IEEE, (2008)Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors., , , , , , , and . CICC, page 1-4. IEEE, (2014)Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2011)Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology., , , , , , , , , and 5 other author(s). ISQED, page 580-584. IEEE, (2013)Sensing margin trend with technology scaling in MRAM., , , , and . I. J. Circuit Theory and Applications, 39 (3): 313-325 (2011)