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Disambiguation of "Dhar, Ashutosh"

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Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling.

, , , , , and . VLSID, page 201-206. IEEE, (2020)

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Ashutosh Banerjee

Ashutosh Trivedi

Ashutosh Malaviya

Ashutosh Modi

Asok Dhar

 

Other publications of authors with the same name

FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache., , , , , , , and . MICRO, page 102-117. IEEE, (2020)WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs., , , , and . ASAP, page 258-265. IEEE, (2021)Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration., and . FCCM, page 48-55. IEEE Computer Society, (2017)NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving., , , , , , , , , and 2 other author(s). ICCAD, page 1-8. ACM, (2019)Reconfigurable and heterogeneous architectures for efficient computing. University of Illinois Urbana-Champaign, USA, (2021)Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications., , , , and . ARC, volume 12700 of Lecture Notes in Computer Science, page 254-264. Springer, (2021)Application-Transparent Near-Memory Processing Architecture with Memory Channel Network., , , , , , , , , and 3 other author(s). MICRO, page 802-814. IEEE Computer Society, (2018)Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads., , , , , , , , and . ISVLSI, page 68-75. IEEE, (2019)Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling., , , , , and . VLSID, page 201-206. IEEE, (2020)A scalable and high-density FPGA architecture with multi-level phase change memory., , and . DATE, page 1365-1370. ACM, (2015)