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Exploration of tradeoffs in the design of integer cosine transforms for image compression.

, , , and . ECCTD, page 1-4. IEEE, (2013)

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A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices., and . DATE, page 1637-1642. IEEE, (2019)Area optimization algorithms in high-speed digital FIR filter synthesis., and . SBCCI, page 64-69. ACM, (2008)Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (6): 1013-1026 (2008)Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications., , , and . DSD, page 3-10. IEEE Computer Society, (2010)Optimization of Area in Digital FIR Filters using Gate-Level Metrics., , , and . DAC, page 420-423. IEEE, (2007)CMOS Implementation of Switching Lattices., , and . DATE, page 274-277. IEEE, (2020)Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications., , , , and . SiPS, page 424-429. IEEE, (2007)Hardware Obfuscation of Digital FIR Filters., , , and . DDECS, page 68-73. IEEE, (2022)Multiplierless Design of Linear DSP Transforms., , , and . VLSI-SoC (Selected Papers), volume 379 of IFIP Advances in Information and Communication Technology, page 73-93. Springer, (2011)Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA., , and . ICCD, page 42-47. IEEE Computer Society, (2014)