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Synchronous Interlocked Pipelines.

, , , , и . ASYNC, стр. 3-12. IEEE Computer Society, (2002)

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Dolores Stanley

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Stanley Heinze

Stanley Durrleman

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Fast Low Power eDRAM Hierarchical Differential Sense Amplifier., и . IEEE J. Solid State Circuits, 44 (2): 631-641 (2009)Design and characteristics of n-channel insulated-gate field-effect transistors., , и . IBM J. Res. Dev., 44 (1): 70-83 (2000)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 486-617. IEEE, (2007)Logic-based eDRAM: Origins and rationale for use., и . IBM J. Res. Dev., 49 (1): 145-166 (2005)Tradeoffs in power-efficient issue queue design., , , , и . ISLPED, стр. 184-189. ACM, (2002)Early-Stage Definition of LPX: A Low Power Issue-Execute Processor., , , , , , , , , и 6 other автор(ы). PACS, том 2325 из Lecture Notes in Computer Science, стр. 1-17. Springer, (2002)Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz., и . IEEE J. Solid State Circuits, 38 (4): 622-630 (2003)A circuit level implementation of an adaptive issue queue for power-aware microprocessors., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 73-78. ACM, (2001)Synchronous Interlocked Pipelines., , , , и . ASYNC, стр. 3-12. IEEE Computer Society, (2002)An Adaptive Issue Queue for Reduced Power at High Performance., , , , , и . PACS, том 2008 из Lecture Notes in Computer Science, стр. 25-39. Springer, (2000)