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Disambiguation of "Iizuka, Tetsuya"

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OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts.

, , and . ISQED, page 776-781. IEEE Computer Society, (2007)

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Tetsuya Takahashi

Hajime Iizuka

Tetsuya Mizutani

Tetsuya Kawata

Tetsuya Takahashi

 

Other publications of authors with the same name

A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS., , and . NEWCAS, page 1-4. IEEE, (2019)A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme., , and . ESSCIRC, page 399-402. IEEE, (2011)Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment., , , , , , and . J. Electron. Test., 34 (2): 147-161 (2018)A calibration-free time difference accumulator using two pulses propagating on a single buffer ring., , , and . A-SSCC, page 1-4. IEEE, (2015)High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (1): 378-388 (2022)INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications., , , , , , , , and . ICTA, page 1-4. IEEE, (2023)140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS., , and . ICICDT, page 73-76. IEEE, (2022)A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter., , , and . VLSI Technology and Circuits, page 10-11. IEEE, (2022)Automatic Visualization Method for Visual Data Mining., , , and . PAKDD, volume 1394 of Lecture Notes in Computer Science, page 173-185. Springer, (1998)An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration., , , and . ICECS, page 231-234. IEEE, (2017)