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Disambiguation of "Takemura, Riichiro"

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2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 43 (1): 109-120 (2008)

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Other publications of authors with the same name

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM., , , , , and . IEEE J. Solid State Circuits, 41 (1): 107-112 (2006)Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device., , , , , , and . ISCAS, page 2299-2302. IEEE, (2012)A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup., , , , , and . ICC, page 1048-1052. IEEE, (2005)Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs., , , , and . CICC, page 1-7. IEEE, (2011)2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 43 (1): 109-120 (2008)A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers., , and . ISLPED, page 123-126. ACM, (2006)Phase change RAM operated with 1.5-V CMOS as low cost embedded memory., , , , , , , , and . CICC, page 431-434. IEEE, (2005)A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing., , , , and . IEICE Trans. Electron., 95-C (4): 600-608 (2012)Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs., and . ICECS, page 739-742. IEEE, (2007)SPRAM (SPin-transfer torque RAM) design and its impact on digital systems., , , and . ICECS, page 1011-1014. IEEE, (2007)