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Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.

, , , , , , , и . ERSA, стр. 81-90. CSREA Press, (2009)

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Herbert Bömelburg

Peter Bömelburg

Thomas Bömelburg

Achim Bömelburg

Hans-Jürgen Bömelburg

 

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Synchronization Processor Synthesis for Latency Insensitive Systems., , и . DATE, стр. 896-897. IEEE Computer Society, (2005)C-based rapid prototyping for digital signal processing., , , , , и . EUSIPCO, стр. 1-4. IEEE, (2005)A formal method for hardware IP design and integration under I/O and timing constraints., , , , и . ACM Trans. Embed. Comput. Syst., 5 (1): 29-53 (2006)High-Level Synthesis in Latency Insensitive System Methodology., , , , , и . DSD, стр. 96-101. IEEE Computer Society, (2005)Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations., и . DSD, стр. 29-36. IEEE Computer Society, (2013)Hardware Discrete Channel Emulator., , , и . HPCS, стр. 452-458. IEEE, (2010)Networked Self-adaptive Systems: An Opportunity for Configuring in the Large., , , , , , , и . ERSA, стр. 81-90. CSREA Press, (2009)Orcc's compa-backend demonstration., , , , , , , , и . DASIP, стр. 1-2. IEEE, (2014)Virtual UARTs for Reconfigurable Multi-processor Architectures., , и . IPDPS Workshops, стр. 252-259. IEEE, (2013)A Networked, Lightweight and Partially Reconfigurable Platform., , и . ARC, том 4943 из Lecture Notes in Computer Science, стр. 314-319. Springer, (2008)