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A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch., , , , , , , , , and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 196-209 (2021)A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path., , , , , , and . ESSCIRC, page 265-268. IEEE, (2023)A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration., , , , , , , , , and 2 other author(s). ESSCIRC, page 499-502. IEEE, (2021)A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR., , , , , , , , , and 4 other author(s). ASP-DAC, page 5-6. IEEE, (2020)A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR., , , , , , , , , and 16 other author(s). ISSCC, page 344-346. IEEE, (2019)A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO., , , , , , , , and . ESSCIRC, page 101-104. IEEE, (2019)A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 55 (9): 2371-2386 (2020)A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 256-258. IEEE, (2019)A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation., , , , , , , , , and 15 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth., , , , , , , , , and 1 other author(s). ISSCC, page 454-456. IEEE, (2021)