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Disambiguation of "Fan, Qingjun"

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A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS.

, , , and . APCCAS, page 30-33. IEEE, (2018)

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Qingjun Xu

Qingjun Ma

Fan Dai

Min Fan

Xiaohua Fan

 

Other publications of authors with the same name

A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC., and . ISCAS, page 1-5. IEEE, (2019)A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications., , , , , and . ISCAS, page 1-4. IEEE, (2020)A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS., , , and . APCCAS, page 30-33. IEEE, (2018)A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration., and . ESSCIRC, page 301-304. IEEE, (2019)RFI mitigating receiver back-end for radiometers., , , , and . IGARSS, page 1255-1258. IEEE, (2017)A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz., , and . ISCAS, page 1-4. IEEE, (2017)Wideband LNA with 1.9 dB noise figure in 0.18 µm CMOS for high frequency ultrasound imaging applications., , , , , , and . NEWCAS, page 1-4. IEEE, (2016)A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS., , , , , and . ISCAS, page 1-4. IEEE, (2019)An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology., , , , , , and . LASCAS, page 1-4. IEEE, (2020)A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology., and . ESSCIRC, page 99-102. IEEE, (2019)