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Disambiguation of "Hsieh, Chih-Cheng"

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8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 58 (1): 303-315 (2023)

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Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

 

Other publications of authors with the same name

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator., and . IEEE J. Solid State Circuits, 54 (6): 1648-1656 (2019)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel., , , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2516-2524 (2021)A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 55 (1): 189-202 (2020)A new cryogenic CMOS readout structure for infrared focal plane array., , and . IEEE J. Solid State Circuits, 32 (8): 1192-1199 (1997)A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS., and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (12): 1171-1175 (2016)A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter., , and . ISCAS, page 2429-2432. IEEE, (2015)A High Performance Linear Current Mode Image Sensor., , and . ISCAS, page 1273-1276. IEEE, (2009)A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC., and . VLSI Circuits, page 1-2. IEEE, (2016)A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique., , and . A-SSCC, page 133-136. IEEE, (2017)