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Diagnosability of delay-deadline failures in fair real time discrete event models.

, , and . Int. J. Syst. Sci., 41 (7): 763-782 (2010)

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Diagnosability of delay-deadline failures in fair real time discrete event models., , and . Int. J. Syst. Sci., 41 (7): 763-782 (2010)SamaTulyataOne: A Path Based Equivalence Checker., , and . ISEC, page 21:1-21:5. ACM, (2019)On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models., , , , , and . Asian Test Symposium, page 88-93. IEEE Computer Society, (2005)Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs., , and . ICSE (2), page 827-828. IEEE Computer Society, (2015)ISBN 978-1-4799-1934-5 (Vol. I + II ???).A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques., , , and . ISED, page 67-71. IEEE, (2012)Validating SPARK: High Level Synthesis Compiler., , and . ISVLSI, page 195-198. IEEE Computer Society, (2015)Verification of Scheduling in High-level Synthesis., , , , and . ISVLSI, page 141-146. IEEE Computer Society, (2006)A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs., , and . SCAM, page 247-252. IEEE Computer Society, (2015)Register Sharing Verification During Data-Path Synthesis., , , and . ICCTA, page 135-140. IEEE Computer Society, (2007)Model checking on state transition diagram., , and . ASP-DAC, page 412-417. IEEE Computer Society, (2004)