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Disambiguation of "Garofalo, Angelo"

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End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.

, , , , , , and . DATE, page 1-6. IEEE, (2023)

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Mauro Garofalo

Pietro Garofalo

Kristin Garofalo

Angelo Geissen

Angelo Schmandra

 

Other publications of authors with the same name

DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs., , , , , and . IEEE Trans. Computers, 70 (8): 1253-1268 (2021)Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs., , , , and . ARCS, volume 12800 of Lecture Notes in Computer Science, page 167-182. Springer, (2021)A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , and . ESSCIRC, page 267-270. IEEE, (2021)ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers., , , , , , and . ISLPED, page 1-6. IEEE, (2023)Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs., , , , , , , , , and 8 other author(s). HCS, page 1-12. IEEE, (2023)Enabling mixed-precision quantized neural networks in extreme-edge devices., , , , and . CF, page 217-220. ACM, (2020)A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference., , , , , and . ISVLSI, page 512-517. IEEE, (2020)Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2450-2463 (2023)XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes., , , , and . CoRR, (2020)A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks., , , , , , , and . ISVLSI, page 1-6. IEEE, (2023)