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Disambiguation of "Chun, Junhyun"

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System Architecture and Software Stack for GDDR6-AiM.

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Dai-Hai Chung

Hae-Bon Chung

Chong-Woon Chung

Myeong-Kee Chung

Ki-Nam Chung

 

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A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)A 0.53pJK2 7000μm2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS., , , , , , , and . ISSCC, page 322-324. IEEE, (2018)A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 56 (6): 1886-1896 (2021)A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 39 other author(s). ISSCC, page 444-446. IEEE, (2022)A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications., , , , , , , , , and 11 other author(s). ISSCC, page 210-212. IEEE, (2018)A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation., , , , , , , , , and 15 other author(s). ISSCC, page 344-346. IEEE, (2021)A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2022)Memory-Centric Computing with SK Hynix's Domain-Specific Memory., , , , , , , , , and 17 other author(s). HCS, page 1-26. IEEE, (2023)A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller., , , , , , , , , and 19 other author(s). ISSCC, page 384-386. IEEE, (2019)