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Disambiguation of "Watanabe, Naoya"

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Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration.

, , , and . 3DIC, page 1-4. IEEE, (2011)

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Wataru Watanabe

Naoya Koseki

Rie Watanabe

Norihiro Watanabe

Shigeo Watanabe

 

Other publications of authors with the same name

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration., , , , , and . 3DIC, page 1-4. IEEE, (2014)Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core., , , , and . 3DIC, page 1-4. IEEE, (2019)Network Testing for Digital Data Networks., , , , , , and . ICC, page 588-592. IEEE, (1986)13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM., , , , , , and . ISSCC, page 240-241. IEEE, (2014)Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs., , , , , , , , and . 3DIC, page 1-4. IEEE, (2019)PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system., , , , , , , , , and 2 other author(s). 3DIC, page 1-4. IEEE, (2011)Evaluation of error recovery schemes for a high-speed packet switched network: link-by-link versus edge-to-edge schemes., and . INFOCOM, page 722-731. IEEE, (1988)Validation of TSV thermo-mechanical simulation by stress measurement., , , , and . Microelectron. Reliab., (2016)A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2671-2680 (2013)High frequency signal transmission characteristics of cone bump interconnections., , and . 3DIC, page 1-5. IEEE, (2011)