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Parallel GF(2n) Modular Squarers., and . MWSCAS, page 872-875. IEEE, (2019)Dadda Multiplier designs using memristors., and . ICICDT, page 1-4. IEEE, (2017)The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)A pipelined architecture for the multidimensional DFT., and . IEEE Trans. Signal Process., 49 (9): 2096-2102 (2001)A scaled DCT architecture with the CORDIC algorithm., and . IEEE Trans. Signal Process., 50 (1): 160-167 (2002)Calculators.. IEEE Ann. Hist. Comput., 17 (3): 75-77 (1995)Calculators.. IEEE Ann. Hist. Comput., 20 (1): 67-76 (1998)A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing., and . ACSSC, page 608-613. IEEE, (2019)A Spanning Tree Carry Lookahead Adder., and . IEEE Trans. Computers, 41 (8): 931-939 (1992)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)