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Bank-Aware Instruction Scheduler for a Multibanked Register File., , , , and . J. Inf. Process., (2018)CNFET7: An Open Source Cell Library for 7-nm CNFET Technology., , , , , and . ASP-DAC, page 763-768. ACM, (2023)An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS., , , , , , and . ISCAS, page 1-5. IEEE, (2023)A Front-End Execution Architecture for High Energy Efficiency., , and . MICRO, page 419-431. IEEE Computer Society, (2014)Isolation-Safe Speculative Access Control for Hardware Transactional Memory., , , , , and . ICECS, page 517-520. IEEE, (2018)Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core., , and . HPC Asia, page 207-216. ACM, (2020)Register Cache System Not for Latency Reduction Purpose., , , and . MICRO, page 301-312. IEEE Computer Society, (2010)The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout., and . ICPE, page 125-132. ACM, (2021)Application of Timing Fault Detection to Rocket Core on FPGA., , and . CANDAR Workshops, page 178-181. IEEE Computer Society, (2018)FXA: Executing Instructions in Front-End for Energy Efficiency., , , and . IEICE Trans. Inf. Syst., 99-D (4): 1092-1107 (2016)