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Disambiguation of "Zhong, Freeman"

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2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS.

, , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 38-39. IEEE, (2014)

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Cecille Freeman

Beau Freeman

Ellis Freeman

Barbara Freeman

Euan Freeman

 

Other publications of authors with the same name

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 49 (12): 3091-3103 (2014)A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS., , , , , , , , , and 15 other author(s). ISSCC, page 348-350. IEEE, (2011)A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 46 (12): 3126-3139 (2011)2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS., , , , , , , , , and 13 other author(s). ISSCC, page 38-39. IEEE, (2014)Integrated Linear AC-coupling Circuit for DC-Balanced and Non-Balanced Traffics., , and . ISCAS, page 2132-2135. IEEE, (2007)A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations., and . ISCAS, page 1400-1403. IEEE, (2013)AC-coupling strategy for high-speed transceivers of 10Gbps and beyond., , , , , , and . VLSI-SoC, page 84-87. IEEE, (2007)A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 47 (10): 2444-2453 (2012)Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS., , , , and . CICC, page 1-4. IEEE, (2010)