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Disambiguation of "Chen, Liang-Gee"

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A 473 μW wireless 16-channel neural recording SoC with RF energy harvester.

, , , , and . VLSI-DAT, page 1-4. IEEE, (2018)

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Liang Chen

Liang Chen

Liang Chen

Liang-chi Chen

Yen-liang Chen

 

Other publications of authors with the same name

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters., , and . VLSI Signal Processing, 40 (2): 175-188 (2005)An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System., , , and . VLSI Signal Processing, 41 (2): 183-191 (2005)Pipeline interleaving design for FIR, IIR, and FFT array processors., , and . VLSI Signal Processing, 10 (3): 275-293 (1995)Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices., , , , and . IEEE Trans. Circuits Syst. Video Techn., 19 (8): 1118-1128 (2009)Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method., , and . APCCAS (1), page 363-366. IEEE, (2002)23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications., , , , , and . ISSCC, page 1-3. IEEE, (2015)Design and implementation of cubic spline interpolation for spike sorting microsystems., , , and . ICASSP, page 1641-1644. IEEE, (2011)Priority depth fusion for the 2D to 3D conversion system., , , , , and . Three-Dimensional Image Capture and Applications, volume 6805 of SPIE Proceedings, page 680513. SPIE, (2008)Automatic threshold decision of background registration technique for video segmentation., , , and . VCIP, volume 4671 of Proceedings of SPIE, page 552-563. SPIE, (2002)The Chip Design of A 32-b Logarithmic Number System., , and . ISCAS, page 167-170. IEEE, (1994)