Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.

H. Zhu, B. Jiao, J. Zhang, X. Jia, Y. Wang, T. Guan, S. Wang, D. Niu, H. Zheng, C. Chen, M. Wang, L. Zhang, X. Zeng, Q. Liu, Y. Xie, and M. Liu. ISSCC, page 1-3. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xiaolong Zhu

Lijun Zhu

Ming Zhu

Nianyong Zhu

Sihong Zhu

Other publications of authors with the same name

OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators.C. Chen, H. Ding, H. Peng, H. Zhu, Y. Wang, and C. Shi. IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 519-530 (2018)A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.X. Jia, H. Zhu, Y. Wang, J. Zhang, F. Lin, X. Xiong, D. Xu, C. Chen, and Q. Liu. ISCAS, page 2816-2820. IEEE, (2022)An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor.X. Cheng, H. Zhu, J. Liu, M. Wang, and X. Zeng. ASICON, page 1-4. IEEE, (2021)A $2.53 W/channel$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.H. Jiang, J. Zheng, Y. Wang, J. Zhang, H. Zhu, L. Lyu, Y. Chen, C. Chen, and Q. Liu. ISCAS, page 1-5. IEEE, (2023)ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test.H. Zhang, H. Zhu, S. He, M. Li, C. Wang, X. Xiong, H. Tian, X. Zeng, and C. Chen. DATE, page 1-6. IEEE, (2024)Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture.H. Zhu, Y. Wang, and C. Shi. IEEE Des. Test, 37 (1): 56-63 (2020)Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation.S. He, H. Zhang, M. Li, H. Zhu, C. Chen, Q. Liu, and X. Zeng. AICAS, page 1-5. IEEE, (2023)A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA.B. Jiao, J. Zhang, Y. Xie, S. Wang, H. Zhu, X. Kang, Z. Dong, L. Zhang, and C. Chen. ASP-DAC, page 13-14. ACM, (2021)TRPN: Matrix Factorization Meets Recurrent Neural Network for Temporal Rating Prediction.H. Zhu, Y. Shen, and X. Zhou. APWeb/WAIM (2), volume 11642 of Lecture Notes in Computer Science, page 57-72. Springer, (2019)A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder.M. Li, H. Zhang, S. He, H. Zhu, H. Zhang, J. Liu, J. Chen, Z. Hu, X. Zeng, and C. Chen. ISCAS, page 1-5. IEEE, (2024)

BibSonomy

Disambiguation of "Zhu, Haozhe"

Please choose a person to relate this publication to

Xiaolong Zhu

Lijun Zhu

Ming Zhu

Nianyong Zhu

Sihong Zhu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhu, Haozhe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.

Please choose a person to relate this publication to

Xiaolong Zhu

Lijun Zhu

Ming Zhu

Nianyong Zhu

Sihong Zhu

Other publications of authors with the same name

Disambiguation