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COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.

, , , , , , , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)

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DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving., , , , and . ISPASS, page 94-104. IEEE Computer Society, (2007)TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization., , , , and . MICRO, page 452-464. ACM, (2023)EPQuant: A Graph Neural Network compression approach based on product quantization., , , , , , and . Neurocomputing, (2022)Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors., and . IEEE Trans. Computers, 59 (8): 1033-1046 (2010)LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures., , , , , , , , , and . CoRR, (2017)Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices., , , and . ISCA, page 255-266. ACM, (2009)Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio., , , , , , , , , and . ICPADS, page 483-490. IEEE, (2022)GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks., , , , , , and . ACA, volume 1256 of Communications in Computer and Information Science, page 73-86. Springer, (2020)FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration., , , and . MASCOTS, page 43-46. IEEE Computer Society, (2015)SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator., , , , , , , , and . MICRO, page 696-709. IEEE Computer Society, (2018)