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Hierarchical Temporal Memory: Concepts, Theory, and Terminology, and . Numenta Inc., (2006)Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments., , , , , and . VTS, page 286-291. IEEE Computer Society, (2001)Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets., , , and . ITC, page 427-435. IEEE Computer Society, (1990)Zero defects or zero stuck-at faults-CMOS IC process improvement with IDDQ., , and . ITC, page 255-256. IEEE Computer Society, (1990)Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ., , , , , and . ITC, page 1051-1059. IEEE Computer Society, (2000)EE Curriculum - Continuous Process Improvement?, and . ITC, page 1118. IEEE Computer Society, (1991)Deep Submicron CMOS Current IC Testing: Is There a Future?, and . IEEE Des. Test Comput., 16 (4): 14-15 (1999)CMOS IC reliability indicators and burn-in economics., , , and . ITC, page 194-203. IEEE Computer Society, (1998)CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations., , , and . ITC, page 423-430. IEEE Computer Society, (1989)Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs., and . ITC, page 443-451. IEEE Computer Society, (1986)