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SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography., , and . ISQED, page 566-571. IEEE, (2013)Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain., , , and . J. Comput. Sci. Technol., 20 (2): 224-230 (2005)A new splitting graph construction algorithm for SIAR router., , , and . ASICON, page 1-4. IEEE, (2013)A novel fine-grain track routing approach for routability and crosstalk optimization., , , , , and . ISQED, page 621-626. IEEE, (2011)Leakage power optimization for clock network using dual-Vth technology., , and . ISCAS, page 2769-2772. IEEE, (2008)Evaluating a bounded slice-line grid assignment in O(nlogn) time., , , , , , and . ISCAS (4), page 708-711. IEEE, (2003)SIAR: splitting-graph-based interactive analog router., , , and . ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2011)A thermal-driven force-directed floorplanning algorithm for 3D ICs., , , and . CAD/Graphics, page 497-502. IEEE, (2009)SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips., , , , and . ISPD, page 49-56. ACM, (2015)Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs., , , and . ASP-DAC, page 582-587. IEEE, (2006)